1. Field of the Invention
The present invention generally relates to the field of integrated circuit technology, and more specifically the invention relates to a monolithically integrated device for ESD (electrostatic discharge) protection of an integrated circuit.
2. Description of Prior Art
Integrated electrostatic discharges may damage electronic devices, particularly electronic semiconductor devices fabricated on insulating or semi-insulating substrates, such as integrated circuits. Devices for protecting against ESD are conventionally incorporated in the input/output paths of most semiconductor devices in order to shunt excessive charge away from the sensitive circuits of the semiconductor devices.
Semiconductor devices are often provided with some protection against high input currents, such as e.g. electrical resistors connected in their input paths, thereby limiting the input current. These resistors are conventionally located outside the bonding pads of the semiconductor devices, thereby occupying valuable chip area.
In U.S. Pat. No. 4,806,999 an integrated circuit is disclosed, which has an input pad protected from electrostatic discharge by two diodes located under the periphery of the pad. One of the diodes is typically formed in an n-tub, and the other in a p-tub. In one embodiment the boundary between the tubs is located in a region not overlaid by the exposed portion of the pad. An input resistor is optionally included between the pad and the input circuitry for additional ESD protection.
In U.S. Pat. No. 4,876,584 an integrated circuit is disclosed, which has a terminal pad protected by a diode directly connected between the pad and a power supply, a transistor directly connected to another power supply, and a resistive path connecting the pad to the remainder of the integrated circuit.
A similar ESD protection structure is disclosed in EP 0 371 663 A1, where the resistor is formed as a metal silicide link located horizontally outside the pad.
Other ESD protection structures including a resistor in an input and/or output path are disclosed in U.S. Pat. Nos. 5,808,343, 5,615,073, 5,196,913, 4,730,208 and 4,710,791.
For high frequency applications at gigahertz frequencies, however, the mentioned resistor creates several problems. The RC product of the circuit input capacitance and the ESD resistor set the limit of the highest operation frequency. Furthermore, the resistance itself creates noise, which is deleterious in low noise applications. It would be highly advantageous for high frequency circuits if the resistor could assume a low value during normal operation and high value during the ESD protection.
A solution to this problem is to provide a varistor in the ESD protection circuit, see WO03/021737. The varistor has a low resistance value while operating in the voltage regime normal for the circuit function and a high resistance value while subject to the voltage exceeding this normal voltage, e.g. during an ESD event. Diodes are connected as current shunting devices. Another similar varistor-based ESD protection circuit is disclosed in U.S. Pat. No. 6,331,726 B1.
While a prior art varistor solution as disclosed in WO03/021737 may provide an increase in the resistance of the varistor of four times when the voltage is increased from 0.5 to 7 V, and may have a capacitance as low as 70 fF, thereby fulfilling high frequency circuit requirements, the series resistance at normal operating voltages may be too high. Calculations have indicated a series resistance of 28 ohm, which may be considered too high for some applications.
One manner to reduce the series resistance is to increase the size of the varistor, but then the parasitic capacitance will increase in turn, which is deleterious for high frequency circuits.